1. Field of the Invention
The present invention relates to a semiconductor device provided with a memory cell array of an open bit line structure or a single-ended structure, and particularly relates to a semiconductor device comprising a configuration in which a plurality of sense amplifiers are arranged at an end of the memory cell array in a zigzag alignment.
2. Description of Related Art
In recent years, an increase in capacity and miniaturization of manufacturing scale have been achieved in a semiconductor device such as DRAM. Therefore, capacitances of bit lines arranged in the memory cell array increase, and thereby measures against an increase in charge/discharge current of the bit lines and a reduction in sensing margin of sense amplifiers are required. Regarding configurations and connection relations of the memory cell array and the sense amplifier, various techniques have been conventionally disclosed (For example, refer to Patent References 1 and 2). The Patent Reference 1 discloses a technique for controlling the connection relation between sense amplifies arranged in the zigzag alignment and bit line pairs divided at an approximate center position in a memory cell array of a folded bit line structure. This technique enables to improve sensing margin and sensing speed of the bit lines through which data is read, and thereby the charge/discharge current of the bit lines in an amplification operation can be reduced by 25 percent. Further, the Patent Reference 2 discloses that when two memory cell arrays of the open bit line structure are selected at the same time, the charge/discharge current can be reduced by 25 percent in an amplification operation of the sense amplifiers by dividing the bit lines of one of the two memory cell arrays at an approximate center position thereof.    [Patent Reference 1] Japanese Patent Application Laid-open No. 5-101643    [Patent Reference 2] Japanese Patent Application Laid-open No. 6-223570 (U.S. Pat. No. 5,426,603)
When the manufacturing scale is miniaturized, pitch of the bit lines arranged in the memory cell array becomes small, and space restriction of circuit arrangement requires the zigzag alignment of the sense amplifiers at both ends of the bit lines. However, since the sense amplifiers in the Patent Reference 2 are not arranged in the zigzag alignment, it is difficult to deal with the miniaturization of manufacturing scale. Therefore, a case of applying a technique obtained by combining the technique of the Patent Reference 2 with the technique of the Patent Reference 1 will be considered. FIG. 16 shows a configuration of a memory cell array in this case. In FIG. 16, a plurality of bit lines BL are alternately connected to sense amplifiers SAe and SAo arranged in the zigzag alignment, and are divided into bit lines BLLe, BLLLo on the left and bit lines BLRe, BLRo on the right by switches Se and So placed at an approximate center position. For example, when an arbitrary word line WLLi of a left area is selected, the switches Se are turned off and the switches So are turned on, so that the bit lines BLRe on the right that are not accessed (non-selected side is represented by dashed lines in FIG. 16) are disconnected from the bit lines BLLe on the left. Here, high-level data is read out to one of two bit lines BLRo adjacent to each disconnected bit line BLRe while low-level data is read out to the other thereof, and a situation is assumed in which the low-level data is written into the bit lines BLRo by inverting the high-level data that has been transmitted to the bit lines BLRo after the amplification operation of the sense amplifiers SAe and Sao. At this point, with the miniaturization of manufacturing scale, a capacitance Cbb between adjacent bit lines BLRe and BLRo becomes large. Thus, the disconnected bit lines BLRe on the right are changed to a negative voltage by coupling noise, and there arises a problem that electric charge leaks from memory cells MC being connected to the bit lines BLRe and storing the high-level data. Therefore, even when the configuration of FIG. 16 is employed, it is difficult to achieve effects of an improvement of the operating margin of the semiconductor device and a reduction in consumption current.